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IRS26310DJPbF
Figure 33: Negative V S transient results for an International Rectifier HVIC
Even though the IRS26310D has been shown able to handle these large negative V S transient conditions, it is highly
recommended that the circuit designer always limit the negative V S transients as much as possible by careful PCB
layout and component use.
PCB Layout Tips
Distance between high and low voltage components: It’s strongly recommended to place the components tied to the
floating voltage pins (V B and V S ) near the respective high voltage portions of the device. The IRS26310D in the
PLCC44 package has had some unused pins removed in order to maximize the distance between the high voltage
and low voltage pins. Please see the Case Outline PLCC44 information in this datasheet for the details.
Ground Plane: In order to minimize noise coupling, the ground plane should not be placed under or near the high
voltage floating side.
Gate Drive Loops: Current loops behave like antennas and are able to receive and transmit EM noise (see Figure
34). In order to reduce the EM coupling and improve the power switch turn on/off performance, the gate drive loops
must be reduced as much as possible. Moreover, current can be injected inside the gate drive loop via the IGBT
collector-to-gate parasitic capacitance. The parasitic auto-inductance of the gate loop contributes to developing a
voltage across the gate-emitter, thus increasing the possibility of a self turn-on effect.
Figure 34: Antenna Loops
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